FINE GRAIN DATA-BASED CLOCK GATING

摘要

Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.

主权项

1. An apparatus, comprising:
a storage circuit configured to:
receive data from a logic circuit; andstore the received data responsive to a clock signal; a comparison circuit configured to compare the received data to data previously stored in the storage circuit; and a clock gating circuit configured to deactivate the clock signal dependent upon the comparison.