MULTI-DIMENSIONAL ERROR DETECTION AND CORRECTION MEMORY AND COMPUTING ARCHITECTURE

摘要

Error correction and detection may be performed across multiple dimensions of memory storage, such as across two or more complete memory devices, as well as within individual pages of memory within a single memory device. Error correction and detection performed across two or more complete memory devices may mitigate single event functional interrupts that affect a complete memory device. Error detection and correction performed within individual pages of memory may be used to mitigate single event upset induced single and multiple bit flips within a page of a memory device. A parallel or serial block code, such as a parallel or serial block Reed-Solomon code or any other type of error correcting code, may be used for error correction and detection performed across two or more complete memory devices or within individual pages of memory within a single memory device.

主权项

1. A processing system, comprising:
a processor module; a memory module coupled to the processor module comprising a plurality of memory devices, each of the memory devices configured to store data in a predefined plurality of memory pages within the device; and an error detection and correction module coupled with the processor module and memory module and configured to perform first error detection and correction encoding on data to be stored across a plurality of the memory devices and second error detection and correction encoding of data to be stored within pages of data to be stored within one or more of the plurality of memory devices.