发明名称 |
DIGITAL PHASE-LOCKED LOOP USING PHASE-TO-DIGITAL CONVERTER, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME |
摘要 |
A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code. |
申请公布号 |
US2014266341(A1) |
申请公布日期 |
2014.09.18 |
申请号 |
US201414182812 |
申请日期 |
2014.02.18 |
申请人 |
JANG Tae Kwang;LIU Jenlung;XING Nan;PARK Jae Jin |
发明人 |
JANG Tae Kwang;LIU Jenlung;XING Nan;PARK Jae Jin |
分类号 |
H03L7/085 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
1. A digital phase locked loop comprising:
a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision, wherein the digital control code is generated based on the quantized code. |
地址 |
Hwaseong-si KR |