SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF INDEXED BARRIERS

摘要

A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.

主权项

1. A method comprising:
initiating execution of a plurality of threads to process instructions of a program that includes a barrier instruction; for each thread in the plurality of threads, pausing execution of instructions when the thread reaches the barrier instruction; determining that the barrier instruction may be scheduled for execution; associating a first sub-group of the threads in the plurality of threads with a first sub-barrier index; associating a second sub-group of the threads in the plurality of threads with a second sub-barrier index; and executing threads in the first sub-group serially and executing threads in the second sub-group serially, wherein at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.