发明名称 LAYOUT BOUNDARY METHOD
摘要 Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
申请公布号 US2014282344(A1) 申请公布日期 2014.09.18
申请号 US201313919037 申请日期 2013.06.17
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Hsu Chin-Hsiung;Chen Wen-Hao;Yu Ho Che
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method to form a cell array on a substrate, comprising: decomposing a cell design into a first layout pattern and a second layout pattern; creating a border around the cell design within the first layout pattern for cell abutment; sharing the border between the cell and an adjacent cell; separating the border into active border shapes and passive border shapes by removing portions of the first layout pattern; and merging a first active shape of the first layout pattern with a passive border shape to reduce area of the cell design.
地址 Hsin-Chu TW