Arbiter for Asynchronous State Machines

摘要

An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

主权项

1. A circuit comprising:
an arbiter configured to:
receive first request signals corresponding to first data signals, wherein each first request signal is associated with a respective first data signal,monitor each of the respective first request signals for activity;latch all corresponding first request signals when activity is detected on at least one of the first request signals,determine which of first request signals have been asserted;transmit data valid signals corresponding to asserted first request signals,transmit a global request signal to a first delay time after the first request signals are latched, andtransmit acknowledge signals corresponding to determined data valid signals.