发明名称 UNIFIED MESSAGE-BASED COMMUNICATIONS
摘要 A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs. Each of the processors is associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via respective hardware unit input and output communication FIFOs. Each of the processors is enabled to send messages to others of the processors via respective processor output communication FIFOs. The respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input communication FIFOs.
申请公布号 US2014281057(A1) 申请公布日期 2014.09.18
申请号 US201313864494 申请日期 2013.04.17
申请人 LSI CORPORATION 发明人 Cohen Earl T.;vonGnechten Mark
分类号 G06F5/06 主分类号 G06F5/06
代理机构 代理人
主权项 1. A system comprising: a plurality of processors, each of the plurality of processors comprising a plurality of communication FIFOs, wherein each of the processors has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs; a message fabric coupling the processors via at least some of the plurality of communication FIFOs; a plurality of hardware units, each of the processors associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via a respective hardware unit input one and via a respective hardware unit output one of the plurality of communication FIFOs; wherein each of the processors is enabled to send messages to others of the processors via respective processor output ones of the plurality of communication FIFOs; and wherein the respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input ones of the plurality of communication FIFOs.
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