| 发明名称 |
INTEGRATED CLOCK DIFFERENTIAL BUFFERING |
| 摘要 |
Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal. |
| 申请公布号 |
US2014266340(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313929164 |
申请日期 |
2013.06.27 |
| 申请人 |
HUANG CHOUPIN;BODDU VIJAYA K.;RUSU STEFAN;PETERSON NICHOLAS B. |
发明人 |
HUANG CHOUPIN;BODDU VIJAYA K.;RUSU STEFAN;PETERSON NICHOLAS B. |
| 分类号 |
H03L7/07 |
主分类号 |
H03L7/07 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. An apparatus comprising:
a first phase locked loop (PLL) circuit having a first clocking ratio coupled to receive an input differential clock signal, the first PLL circuit to generate a first reference clock signal; a second PLL circuit having a second clocking ratio coupled to receive the input differential clock signal, the second PLL circuit to generate a second reference clock signal; a first set of clock signal output buffers coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal; a second set of clock signal output buffers coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal; wherein the first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal. |
| 地址 |
San Jose CA US |
