| 摘要 |
An integrated circuit chip including: a chip pin configured to direct signals on and off chip; a first signal path from the chip pin to a first electrostatic discharge (ESD) susceptible circuit susceptible to a voltage greater than a first voltage level; a first protection circuit coupled to a first node on the first signal path, the first protection circuit being operable to limit the voltage of a signal directed on chip to a second voltage level, the second voltage level being higher than the first voltage level; and a second protection circuit coupled to a second node on the first signal path between the first node and the first ESD susceptible circuit, the second protection circuit being operable to limit the voltage of the signal directed on chip to the first voltage level. |
