发明名称 Memory system
摘要 Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information.
申请公布号 US8838879(B2) 申请公布日期 2014.09.16
申请号 US201113238191 申请日期 2011.09.21
申请人 Kabushiki Kaisha Toshiba 发明人 Yoshida Norikazu
分类号 G06F13/00;G06F13/28;G06F12/06 主分类号 G06F13/00
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory system comprising: a plurality of nonvolatile memory banks commonly coupled to a data input/output line, and capable of performing an interleaving operation, a data cache and a memory cell array disposed inside each of the plurality of nonvolatile memory banks, data being read out from the memory cell array by a page unit and then stored in the data cache; a first controller configured to generate a plurality of page read commands by dividing a read request by the page unit, and to allocate the plurality of page read commands, in accordance with bank addresses specified by the page read commands, to a plurality of read queues provided respectively for the plurality of nonvolatile memory banks; a second controller including a plurality of bank controllers respectively coupled with the plurality of read queues, each of the plurality of bank controllers configured to issue the page read commands to the corresponding nonvolatile memory bank in parallel, regardless of an order of logical addresses specified by the page read request; and a third controller configured to control the second controller so that data stored in the data caches of the plurality of nonvolatile memory banks are sequentially transferred to outside the memory system through the data input/output line in accordance with the order of logical addresses specified by the read request, wherein the data cache is used for separating the data transfer stage from the data reading stage, thereby a data reading operation is performed in parallel among the plurality of nonvolatile memory banks and a data transferring operation from the plurality of nonvolatile memory banks to outside the memory system is performed, without using another memory component, in accordance with the order of logical addresses specified by the read request.
地址 Tokyo JP