Advance clocking scheme for ECC in storage

摘要

A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.

主权项

1. A system for clocking a decoder, comprising:
a channel front end configured to receive input data; a first clock configured to provide a first clock signal as input to the channel front end; a decoder configured to receive intermediate data associated with the output of the channel front end; a second clock configured to provide a second clock signal as input to the decoder, wherein the second clock signal is not derived from the first clock signal; and a clock controller coupled to the input to the second clock, wherein the clock controller is configured to adjust the second clock frequency based at least in part on error information associated with the input data.