| 摘要 |
The present invention discloses a multi-phase switching regulator and a control method thereof. The multi-phase switching regulator includes plural power stage circuits, wherein at least one power stage circuit is enabled or disabled according to a phase adding/shedding signal; at least one zero current detection circuit, which is coupled to one of the power stage circuit, for generating a trigger signal according to an inductor current in a corresponding one of the power stage circuits, a zero current reference signal, and an average reference signal; and a phase control circuit controlling the phase adding/shedding operation according to the trigger signal. |
| 主权项 |
1. A multi-phase switching regulator, comprising:
a plurality of power stage circuits, for converting an input voltage to an output voltage, wherein at least one power stage circuit is enabled or disabled according to a phase adding/shedding signal; at least one zero current detection circuit, which is coupled to a corresponding one of the power stage circuit, for generating a trigger signal according to an inductor current which is generated by the corresponding power stage circuit, a zero current reference signal, and an average reference signal; and a phase control circuit, which is coupled to the at least one power stage circuit and the zero current detection circuit, for generating the phase adding/shedding signal according to the trigger signal to enable or disable the at least one power stage circuit; wherein when the inductor current is not higher than the zero current reference signal for a first predetermined time period, the phase adding/shedding signal disables the at least one power stage circuit; wherein when the inductor current is higher than the average reference signal for a second predetermined time period, the phase adding/shedding signal enables the at least one power stage circuit;wherein the zero current detection circuit includes:
a first comparator circuit, which is coupled to the corresponding power stage circuit, for generating a first comparison signal according to the inductor current and the zero current reference signal; a first timer circuit, which is coupled to the first comparator circuit, for generating a phase shedding trigger signal when the inductor current is not higher than the zero current reference signal for the first predetermined time period, such that the phase adding/shedding signal disables the at least one power stage circuit; a second comparator circuit, which is coupled to the corresponding power stage circuit, for generating a second comparison signal according to the inductor current and the average reference signal; and a second timer circuit, which is coupled to the second comparator circuit, for generating a phase adding trigger signal when the inductor current is higher than the average reference signal for the second predetermined time period, such that the phase adding/shedding signal enables the at least one power stage circuit. |
