Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline

摘要

Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.

主权项

1. A circuit arrangement, comprising:
a processing unit including a fixed point execution unit and a vector floating point unit, the fixed point execution unit including a plurality of general purpose registers configured to be accessed by the fixed point execution unit, and the vector floating point unit including a vector register file configured to be accessed by the vector floating point unit, wherein the fixed point execution unit and the vector floating point unit are separate from one another; wherein the processing unit is configured to cache state data including non-floating point state data used by the fixed point execution unit in the vector register file, wherein the processing unit is further configured to copy the non-floating point state data from the vector register file to at least one general purpose register among the plurality of general purpose registers, and wherein the fixed point execution unit is configured to operate on the non-floating point state data stored in the at least one general purpose register.