Divider logic circuit and implement method therefor

摘要

A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N1−N, and the exponent is i−1; wherein the right shift registers shift the first constant value to the right for h*i-digit for outputting a second constant value; wherein the multiplier multiplies a third constant value by the constant value M−N*S1 for outputting a fourth constant value, wherein the first adder adds up the estimate S1 and the fourth constant value for outputting the quotient S. The present invention also provides an implement method therefor.

主权项

1. A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, comprising:
a first constant value input terminal for inputting an estimate value S1 of the quotient S; a first adder connected with said first constant value input terminal; a second constant value input terminal for inputting a constant value M−N*S1; a base number input terminal for inputting a base number N1−N; at least one integer power device connected with said base number input terminal; at least one right shift register connected with said integer power device; a second adder connected with said right shift register, and a multiplier connected with said first adder, said second adder and said second constant value input terminal, wherein N1 is a standard power value which is the closest to said divisor N, N1=2h, wherein h is a natural number, wherein said integer power device determines a first constant value that said base number is N1−N, and an exponent is i−1, wherein i is a natural number, wherein said right shift register shifts said first constant value determined by said integer power device to the right for h*i-digit for outputting a second constant value to said second adder, wherein said multiplier multiplies a third constant value that said second adder outputs by said constant value M−N*S1 inputted by said second constant value input terminal for outputting a fourth constant value to said first adder, wherein said first adder adds up said estimate S1 inputted by said first constant value input terminal and said fourth constant value sent by said multiplier and outputs said quotient S of said dividend M divided by said divisor N.