Systems and methods for reduced coupling between digital signal lines

摘要

Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.

主权项

1. A digital data output system, comprising:
data storage circuitry configured to store two or more data bits and to output the data bits in sequence based upon a clock signal; and output circuitry coupled to receive a current data bit and a next data bit from the data storage circuitry; wherein the output circuitry is configured to output a low logic level for a clock cycle when the current data bit is a low logic level; and wherein the output circuitry is further configured to output a high logic level during a first portion of a clock cycle when the current data bit is a high logic level, to maintain the high logic level for the clock cycle if the next data bit is a high logic level, and to transition to a low logic level during the clock cycle if the next data bit is a low logic level.