发明名称 Method for creating a 3D stacked multichip module
摘要 A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
申请公布号 US8836137(B2) 申请公布日期 2014.09.16
申请号 US201213451411 申请日期 2012.04.19
申请人 Macronix International Co., Ltd. 发明人 Chen Shih-Hung
分类号 H01L23/48;H01L23/52;H01L21/00 主分类号 H01L23/48
代理机构 Haynes Beffel & Wolfeld LLP 代理人 Hann James F.;Haynes Beffel & Wolfeld LLP
主权项 1. A three-dimensional stacked multichip module comprising: a stack of integrated circuit die including W integrated circuit die, W being an integer greater than 1, each of the W integrated circuit die in the stack comprising a patterned conductor layer over a substrate, the patterned conductor layer comprising an electrical contact region, the electrical contact region comprising electrical conductors, at least one of the electrical conductors comprising a landing pad; the stack of die comprising a first die at one end of the stack and a second die at the other end of the stack, the substrate of the first die facing the patterned conductor layer of the second die; the landing pads on each die being aligned with those on the other die in the stack; W electrical connectors extending from a surface of the stack of die and into the stack of die to electrically contact the landing pads on the W integrated circuit die, to create a three-dimensional stacked multichip module having W die levels, the electrical connectors comprising lengths of substantially homogeneous electrically conductive material which lack physical boundaries between the die levels; and each of the W electrical connectors being electrically connected to one landing pad of one die level.
地址 Hsinchu TW
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