Non-volatile semiconductor device, and method of operating the same

摘要

A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.

主权项

1. A method of operating a non-volatile semiconductor device, the non-volatile semiconductor device comprising a gate dielectric layer formed on a n-type semiconductor substrate; a p-type floating gate formed on the gate dielectric layer; a first p-type source/drain and a second p-type source/drain formed in the n-type semiconductor substrate and disposed at opposing sides of the p-type floating gate; a first contact plug formed on the first p-type source/drain; a second contact plug formed on the second p-type source/drain; and at least one coupling gate consisting essentially of a capacitor dielectric layer and a third contact plug, wherein the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer, and the method comprising:
applying a first programming electrical potential to the first conductive plug; applying a second programming electrical potential to the second conductive plug; applying a third programming electrical potential to the third conductive plug; applying a fourth programming electrical potential to the n-type semiconductor substrate, wherein the second programming electrical potential is less than the third programming electrical potential; applying a first reading electrical potential to the first conductive plug; applying a second reading electrical potential to the second conductive plug; applying a third reading electrical potential to the third conductive plug; and applying a fourth reading electrical potential to the n-type semiconductor substrate, wherein the first reading electrical potential is approximately equal to the fourth reading electrical potential, each of the first and fourth reading electrical potentials is less than the second reading electrical potential, and each of the first and fourth reading electrical potentials is greater than the third reading electrical potential.