发明名称 |
Nonvolatile semiconductor memory device and read method for the same |
摘要 |
A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory. |
申请公布号 |
US8837200(B2) |
申请公布日期 |
2014.09.16 |
申请号 |
US201213700346 |
申请日期 |
2012.06.18 |
申请人 |
Panasonic Corporation |
发明人 |
Tsuji Kiyotaka;Shimakawa Kazuhiko |
分类号 |
G11C11/00;G11C13/00 |
主分类号 |
G11C11/00 |
代理机构 |
Wenderoth, Lind & Ponack, LLP |
代理人 |
Wenderoth, Lind & Ponack, LLP |
主权项 |
1. A nonvolatile semiconductor memory device comprising:
word lines formed in parallel in a first plane; bit lines formed in parallel in a second plane and three-dimensionally crossing the word lines, the second plane being parallel to the first plane; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines, wherein the cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines; and an offset detection cell having a resistance value that is, irrespective of an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines, higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory. |
地址 |
Osaka JP |