CMOS dual metal gate semiconductor device

摘要

A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

主权项

1. A semiconductor structure comprising:
a semiconductor substrate; a first MOS device of a first conductivity type, the first MOS device comprising:
a first gate dielectric over the semiconductor substrate;a first metal-containing gate electrode layer over the first gate dielectric;a silicon-containing layer over and contacting the first metal-containing gate electrode layer; anda first contact etch stop layer having a first portion directly over the silicon-containing layer; and a second MOS device of a second conductivity type opposite the first conductivity type, the second MOS device comprising:
a second gate dielectric over the semiconductor substrate;a second metal-containing gate electrode layer over the second gate dielectric, wherein a top surface of the first metal-containing gate electrode layer is lower than a top surface of the second metal-containing gate electrode layer; anda second contact etch stop layer having a second portion directly over the second metal-containing gate electrode layer, wherein no silicon-containing layer is disposed directly over the second metal-containing gate electrode layer and under the second contact etch stop layer.