发明名称 |
Method of manufacturing a semiconductor memory device |
摘要 |
According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer. |
申请公布号 |
US8835241(B2) |
申请公布日期 |
2014.09.16 |
申请号 |
US201313751803 |
申请日期 |
2013.01.28 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Ishibashi Yutaka;Hayashi Katsumasa;Sonoda Masahisa |
分类号 |
H01L21/8238;H01L45/00;H01L27/24;H01L49/02;H01L27/10 |
主分类号 |
H01L21/8238 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A method of manufacturing a semiconductor device, comprising:
forming a first interlayer insulating film; forming a lower-layer wire on the first interlayer insulating film; forming a storage layer and a conductive layer on the lower-layer wire; processing the conductive layer, the storage layer, and the lower-layer wire down to the first interlayer insulating film to form a trench; burying and forming a second interlayer insulating film in the trench; first etching back the second interlayer insulating film by a CMP method using the conductive layer as a stopper; second etching back a top surface of the second interlayer insulating film by a different process than the CMP method of the first etching back, to be lower than a top surface of the conductive layer; and forming an upper-layer wire on the second interlayer insulating film and on the conductive layer. |
地址 |
Minato-ku JP |