Clock selection circuit and method

摘要

The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

主权项

1. A clock select circuit for providing a selected clock signal to its output, comprising:
a first branch, which includes a first latch clocked by a first clock signal, the first branch having a logic gate at the output for passing the first clock signal to the circuit output in dependence on the first latch output; a second branch, which includes a second latch clocked by a second clock signal, the second branch having a logic gate at the output for passing the second clock signal to the circuit output in dependence on the second latch output; a first feedback arrangement from the output of the first latch to the second branch before the second latch; a second feedback arrangement from the output of the second latch to the first branch before the first latch; and an override circuit provided in the first or second feedback arrangements for preventing a latching delay in that feedback arrangement.