Device packaging with substrates having embedded lines and metal defined pads

摘要

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

主权项

1. A method for assembly of an IC chip to a package substrate, the method comprising:
providing an IC chip having an plurality of IC chip connection points each of said IC chip connection points having solder disposed thereon; providing a package substrate having a plurality of package substrate connection points, each of said package connection points having a surface-level metal feature comprising a fill metal embedded in a surface level dielectric, said surface-level dielectric disposed between adjacent package substrate connection points, each of said package substrate connection points having a surface finish metal formed on said fill metal and protruding beyond the top surface of said surface-level dielectric, said package substrate further comprising a metal trace embedded within said surface-level dielectric between two of said package substrate connection points; aligning the IC chip connection points with the package substrate connection points; and alloying the solder on the IC chip connection points with the surface finish metal on the package substrate connection points to affix the IC chip connection points to the package substrate connection points.