Shared non-volatile storage for digital power control

摘要

Systems and methods may be implemented in a power device subsystem topology to provide an arbitration and communication scheme between a single consolidated non-volatile random access (NVRAM) memory device and multiple discrete digital power controller devices in a manner that provides data protection and the ability to update the full NVRAM content when needed.

主权项

1. An information handling system comprising:
multiple power-consuming circuitry components or systems; multiple digitally controlled voltage regulation components coupled to separately regulate power provided to individual power-consuming circuitry components or systems, or to a subgroup of the individual power-consuming circuitry components or systems; multiple digital power controller devices, each of the multiple digital power controller devices being coupled to one or more of the digitally controlled voltage regulation components to separately control the power provided to individual power-consuming circuitry components or systems, or to a subgroup of the individual power-consuming circuitry components or systems; and shared non-volatile memory (NVRAM), each of the multiple digital power controller devices being coupled to access the shared NVRAM by a communication topology configured to provide shared access for the multiple digital power controller devices to the shared NVRAM; where the communication topology comprises at least one shared bus coupled between the shared NVRAM and each of the digital power controller devices; and where the information handling system further comprises at least one processing device configured as an arbiter device to arbitrate between the multiple digital power controller devices to allow sole access across the shared bus to the shared NVRAM by only one of the multiple digital power controller devices at any given time; and where the information handling system further comprises a service processor communicatively coupled to the arbiter processing device and to each of the multiple digital power controller devices, the service processor being configured to change an arbitration pattern used by the arbiter device to arbitrate between the multiple digital power controller devices to allow sole access to the shared NVRAM by only one of the multiple digital power controller devices at any given time.