Use of logic circuit embedded into comparator for foreground offset cancellation

摘要

A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

主权项

1. A system for cancelling an offset of a comparator, the system comprising:
the comparator, wherein all input terminals to the comparator are switchable to a reference signal; a logic circuit receiving an output from the comparator and generating a digital codeword locally based on the output from the comparator; and a digital to analog converter (“DAC”) that receives that digital codeword and injects a calibration current or voltage at designated injection points in the comparator to cancel the offset, wherein the designated injection points are other than the input terminals to the comparator.