发明名称 |
Self-aligned double patterning via enclosure design |
摘要 |
A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so. |
申请公布号 |
US8839168(B2) |
申请公布日期 |
2014.09.16 |
申请号 |
US201313746508 |
申请日期 |
2013.01.22 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Kye Jongwook;Levinson Harry J;Stephens Jason E;Yuan Lei |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Keohane & D'Alessandro, PLLC |
代理人 |
Pogue Darrell L.;Keohane & D'Alessandro, PLLC |
主权项 |
1. A method for computing via enclosure rules, comprising:
identifying, by at least one computing device, line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias; assigning, by the at least one computing device, a first via enclosure rule in response to identifying a line termination mode of inner vertex block mask, wherein the inner vertex block mask comprises at least one vertex that has an outer angle that is less than 180 degrees; and assigning, by the at least one computing device, a second via enclosure rule in response to identifying a line termination mode of outer vertex block mask, wherein the outer vertex block mask consists of vertices that have an outer angle that is greater than 180 degrees. |
地址 |
Grand Cayman KY |