Nonvolatile memory and manipulating method thereof

摘要

A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

主权项

1. A manipulating method of a nonvolatile memory, comprising:
providing the nonvolatile memory having a plurality of memory cell, two adjacent memory cells of the memory cells correspond to one bit, the two adjacent memory cells comprising a substrate, a first doping region and another first doping region, a second doping region disposed between the first doping region and the another first doping region, a charge trapping layer, a control gate disposed on the charge trapping layer, a first bit line coupling to the first doping region, a source line coupling to the second doping region and a second bit line coupling to the another first doping region, wherein the first bit line and the second bit line are different, a first channel formed between the first doping region and the second doping region, and a second channel formed between the second doping region and the another first doping region, the charge trapping layer disposed on the first channel and the second channel; and programming the two adjacent memory cells, comprising:
applying a first positive voltage to the control gate between the first doping region and the second doping region;applying a first negative voltage to the control gate between the second doping region and the another first doping region; andapplying a first voltage to the source line, so that a voltage level of the source line is larger than a voltage level of the first bit line and a voltage level of the second bit line.