Engineering change order hold time fixing method

摘要

An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.

主权项

1. A computer-based engineering change order hold time fixing method executed by using a non-transitory computer readable medium for fulfilling a short path padding in a placed and routed design by a minimum capacitance insertion, comprising:
a padding value determination step, which receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output; and a load/buffer allocation step, which is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design; wherein the padding value determination step comprises: a padding resource collection step, which is based on the spare cell information, the dummy metal information to collect available spare cells and available dummy metal information located within a bounding box of a fanout net of a gate in the placed and routed design; a fanout padding flexibility calculation/flexibility checking step, which calculates a fanout padding flexibility PF(gi) of the gate gi in the placed and routed design; a padding value decision step, which is based on the fanout adding flexibility PF(gi) of the gate gi to calculate a padding value of the gate; an improvement determination step, which determines whether all hold violations of short paths of each gate in the placed and routed design are resolved or no more violation is eliminated, and returns to the fanout padding flexibility calculation/flexibility checking step when a violation is not resolved or eliminated; and a padding value refinement step, which is based on a reverse topological order to calculate a refined padding value of the gate in the placed and routed design when all hold violations of short paths of each gate in the placed and routed design are resolved or no more violation is eliminated, so as to further reduce the padding value of the gate; and wherein the load/buffer allocation step comprises: a finding spare cell candidate step, which generates spare cell candidates for each padding gate/wire in the placed and routed design, such that for each padding gate, the available spare cells located within the bounding box of the fanout net are programmed as an available resource for a padding gate; a spare cell selection step, which assigns an optimal subset sum solution to each padding gate/wire to completely pad the short paths in the placed and routed design; and a dummy metal allocation step, which use a dummy metal insertion to completely pad the short paths in the placed and routed design; and wherein the placed and routed design is represented by a directed graph K=(G, E), where K is comprised of gates G and edges E, each node gi∈G represents a gate associated with a gate delay D(gi), and each edge e(gi, gj)∈E represents a wire connecting the gates gi, gj∈G, such that a setup arrival time A(gi) of an output of the node gi is expressed as:
A(gi)=maxj{A(gj)|e(gi, gj)∈E}+D(gi),a setup required time R(gi) of the output of the node gi is expressed as:
R(gi)=mink{R(gi, gk)|R(gi, gk)=R(gk)−D(gk), e(gi, gk)∈E},a hold arrival time a(gi) of the output of the node gi is expressed as:
a(gi)=minj{a(gj)|e(gj, gi)∈E}+D(gi), anda hold required time r(gi) of the output of the node gi is expressed as:
r(gi)=mink{r(gi, gk)|r(gi, gk)=r(gk)−D(gk), e(gi, gk)∈E}.