High-k dielectric device and process

摘要

An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.

主权项

1. A method for fabricating a MOS transistor in a semiconductor substrate having a first conductivity type comprising:
forming source and drain regions by implanting in the semiconductor substrate ions having a second conductivity type; forming an insulating layer on an upper surface of the semiconductor substrate; removing a portion of the insulating layer to form a hole that exposes the upper surface of the semiconductor substrate between the source and drain regions; forming a spacer layer on an upper surface of the insulating layer, on sidewalls of the hole in the insulating layer and on the exposed upper surface of the semiconductor substrate; forming spacers by anistropically etching the spacer layer so as to remove the spacer layer on the upper surface of the semiconductor substrate, thereby exposing the upper surface of the semiconductor substrate, and to remove a portion of the spacer layer on the sidewalls of the insulating layer; forming a high-k dielectric layer between the spacers on the exposed upper surface of the semiconductor substrate; and forming a gate on the portion of the high-k dielectric layer formed between the spacers on the exposed upper surface of the semiconductor substrate; wherein a top surface of the gate is substantially co-planar with a top surface of the insulating layer.