Semiconductor integrated circuit and pattern layouting method for the same

摘要

A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

主权项

1. A semiconductor integrated circuit comprising:
functional areas formed within a chip and including scribing areas, module areas and an I/O area; and a dummy pattern formed in a space area within the chip, the space area being defined between the functional areas, within any of the functional areas, and/or at a position spanning an area where any of the functional areas is formed and an area formed with none of the functional areas, the dummy pattern including: a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern; a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion; and a plurality of non-forming areas positioned on the inner periphery side of the first metal portion in an area where the second metal portion is not formed.