发明名称 Methods for the formation of a trap rich layer
摘要 An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
申请公布号 US8835281(B2) 申请公布日期 2014.09.16
申请号 US201313919947 申请日期 2013.06.17
申请人 Silanna Semiconductor U.S.A., Inc. 发明人 Brindle Chris;Stuber Michael A.;Molin Stuart B.
分类号 H01L21/30 主分类号 H01L21/30
代理机构 The Mueller Law Office, P.C. 代理人 The Mueller Law Office, P.C.
主权项 1. A process for manufacturing an integrated circuit comprising: forming a circuit layer in a semiconductor wafer, said semiconductor wafer having a substrate and an exposed substrate surface; depositing a layer of polysilicon on a second semiconductor wafer; and bonding said second semiconductor wafer to an opposite surface of said semiconductor wafer, said opposite surface being on an opposite side of said semiconductor wafer from said exposed substrate surface; wherein said layer of polysilicon forms a trap rich layer; and wherein said trap rich layer remains in a finished structure for said integrated circuit.
地址 San Diego CA US