发明名称 |
CMOS integrated circuit and amplifying circuit |
摘要 |
There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit. |
申请公布号 |
US8836429(B2) |
申请公布日期 |
2014.09.16 |
申请号 |
US201213612428 |
申请日期 |
2012.09.12 |
申请人 |
Samsung Electro-Mechanics Co., Ltd. |
发明人 |
Murakami Tadamasa |
分类号 |
H03F3/16;H03K19/0948;H01L27/12;H03F1/52;H01L29/78;H03F3/193;H01L21/761;H01L27/092;H01L27/13;H01L27/06 |
主分类号 |
H03F3/16 |
代理机构 |
McDermott Will & Emery LLP |
代理人 |
McDermott Will & Emery LLP |
主权项 |
1. A complementary metal-oxide-semiconductor (CMOS) integrated circuit, comprising a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal,
the field effect transistor being formed on a silicon on insulator (SOI) substrate and a connection between a body potential and a potential lower than a source potential being formed by a resistor element, wherein the resistance value of the resistor element is 10 times that of an R value satisfying Equation 1 below,R=1ωCgb=12πfCgb[Equation1] where Cgb is gate-body parasitic capacitance and to is angular frequency of signal inputted to the field effect transistor. |
地址 |
Suwon, Gyunggi-Do KR |