| 发明名称 |
Circuits and methods for measuring circuit elements in an integrated circuit device |
| 摘要 |
A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section. |
| 申请公布号 |
US8837230(B1) |
申请公布日期 |
2014.09.16 |
| 申请号 |
US201314072761 |
申请日期 |
2013.11.05 |
| 申请人 |
Suvolta, Inc. |
发明人 |
Clark Lawrence T.;Roy Richard S. |
| 分类号 |
G11C7/00;G01R31/27;G11C7/10 |
主分类号 |
G11C7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory circuit device having at least one test element interconnecting memory sections, the test element comprising:
at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section. |
| 地址 |
Los Gatos CA US |
