| 摘要 |
Disclosed are an integrated level shifting latch circuit which receives an input signal in a first voltage domain and generates an output signal in a second voltage domain, and a method for operating the same. The latch circuit includes a data retention circuitry operating in the second voltage domain and configured to operate in a transparent phase where a data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is retained irrespective of any change in the input signal during the latching phase, and that retained data value forms the output signal. A control circuit receives a clock signal and controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal, and to operate in the latching phase during a second phase of the clock signal. A writing circuit writes the data value into the data retention circuitry by controlling a voltage of at least one internal node of the data retention circuitry dependent on the input signal during the transparent phase. A contention mitigation circuit receives an input signal and, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry, thereby assisting the writing circuitry in altering the voltage of the internal node during the transparent phase. In particular, the present invention provides a high performance solution where both of an area and power are efficient, and variation between a voltage at the first voltage domain and a voltage at the second voltage domain is significantly operated. |
