LOW GLITCH-NOISE DAC

摘要

An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M-1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N-M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N-M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.