发明名称 SELF-TESTING INTEGRATED CIRCUITS
摘要 <p>In an example, a self-testing integrated circuit (IC) includes N channels i and a controller, where i is an integer from 1 to N. Each channel i may include a clock and data recovery circuit (CDR), a pseudorandom bit stream (PRBS) generator circuit, and a PRBS checker and eye quality monitor (EQM) circuit. The controller may be configured to selectively couple the channels i in a daisy chain during self-testing.</p>
申请公布号 WO2014138681(A1) 申请公布日期 2014.09.12
申请号 WO2014US22093 申请日期 2014.03.07
申请人 FINISAR CORPORTION 发明人 NGUYEN, THE LINH
分类号 G01R31/3187;G01R31/3185;G01R31/319;G06F11/27 主分类号 G01R31/3187
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