Last Branch Record Indicators For Transactional Memory

摘要

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

主权项

1. A processor comprising:
an execution unit; a plurality of last branch record (LBR) registers each to store at least one of source and destination address information of a branch taken during program execution, each of the plurality of LBR registers further including a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction; and a logic to allocate one of the plurality of LBR registers responsive to a first instruction.