| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces the occurrence of a parasitic capacitance.SOLUTION: The semiconductor device includes: an Si substrate with an ESD protection circuit formed; a pad P1 formed on a surface of the Si substrate; and a rewiring layer formed on a surface of the ESD protection circuit. The rewiring layer has a first wiring electrode 232 overlapping the pad P1 in a plan view and having continuity to the pad P1 via a first interlayer connection conductor 231, a second planar wiring electrode 252 overlapping a part of the first planar wiring electrode 232 spaced from the first interlayer connection conductor 231 in the plan view, and formed on the opposite side to the Si substrate in a thickness direction of the rewiring layer, and a second interlayer connection conductor 251 establishing continuity between the first planar wiring electrode 232 and the second planar wiring electrode 252. The diameter &phgr;2 of the second interlayer connection conductor 251 is smaller than the diameter &phgr;1 of the first interlayer connection conductor 231, and the first planer wiring electrode 232 has a smaller area on the side of the second interlayer connection conductor 251 than on the side of the first interlayer connection conductor 231. |
