DIFFERENTIAL AMPLIFIERS, CLOCK GENERATOR CIRCUITS, DELAY LINES AND METHODS

摘要

A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.

主权项

1. A clock generator, comprising:
an input buffer configured to receive a clock signal at a signal input node and to output the clock signal at an output node; a delay line having an input node coupled to the output node of the input buffer, an output node, a delay control node, and a duty cycle control node, the delay line being configured to be responsive to a delay control signal applied to the delay control node to adjust a delay of the delay line and to be responsive to a duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of the clock signal being coupled through the delay line; a phase detector having a first input node coupled to the signal output node of the delay line, a second input node coupled to receive the clock signal applied to the signal input node of the input buffer, and an output node coupled to the delay control node, the phase detector being configured to provide the delay control signal at the output node corresponding to a phase difference between a signal applied to the first input node and the clock signal applied to the second input node; and a duty cycle control circuit having an input node coupled to the output node of the delay line and an output node coupled to the duty cycle control node of the delay line, the duty cycle control circuit being configured to provide at the output node the duty cycle control signal corresponding to the duty cycle of the clock signal being coupled through the delay line from the input node of the delay line to the output node of the delay line.