GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS

摘要

A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

主权项

1. A method of forming a semiconductor device comprising:
forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate; forming a scavenging metal stack on the high-k gate dielectric layer, wherein the forming of the scavenging metal stack on the high-k gate dielectric layer comprises:
forming a first metal nitride layer on the high-k gate dielectric layer;forming a scavenging metal layer on the first metal nitride layer; andforming a second metal nitride layer on the scavenging metal layer; performing an anneal process during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material; removing the scavenging metal stack; forming a gate conductor layer of a semiconducting material on the high-k gate dielectric layer; patterning the gate conductor layer of the semiconducting material and the high-k gate dielectric layer to provide a gate structure; and forming a source region and a drain region on opposing sides of the gate structure.