| 发明名称 |
PIPELINED PROCESSOR |
| 摘要 |
Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer. |
| 申请公布号 |
US2014258682(A1) |
申请公布日期 |
2014.09.11 |
| 申请号 |
US201313895937 |
申请日期 |
2013.05.16 |
| 申请人 |
Advanced Digital Chips Inc. |
发明人 |
CHA YOUNG HO;LEE KWANG HO;KIM KWAN YOUNG;MIN BYUNG GUEON |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor with a multi-pipeline fetch structure or a multi-cycle cache structure, comprising:
an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer. |
| 地址 |
Gyeonggi-do KR |
