METHOD FOR HIDING TEXTURE LATENCY AND MANAGING REGISTERS ON A PROCESSOR

摘要

The invention relates to a method for hiding texture latency in an MVP processor, which comprises the following steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with same length, and binding the register sets to the dies at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a PC (Program Counter) value in the case of return; and returning texture detail and allowing the shader thread to restart running. The invention also relates to a method for managing registers of grahic processing threads in the MVP processor.

主权项

1. A method for hiding texture latency in an MVP processor, comprising the following steps of:
A) allowing the MVP processor to start running a main rendering program, closing hardware interrupt enable for all the threads for rendering processing, and disabling hardware interrupt for all the threads; B) segmenting registers of various MVP kernel instance in the MVP processor according to the length set, acquiring a plurality of register sets with same length, and binding the register sets to the dies of the MVP; C) allowing a shader thread to give up a processing time slot occupied by the shader thread to a backup thread in a waiting queue to run after sending a texture detail request; and D) returning texture detail and allowing the shader thread to wait for an idle processing time slot and restart running at a position pointed by a PC (Program Counter) value.