发明名称 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
摘要 Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate.
申请公布号 US2014252605(A1) 申请公布日期 2014.09.11
申请号 US201414198713 申请日期 2014.03.06
申请人 Samsung Electronics Co., Ltd. 发明人 MA Keum-Hee;JO Cha-Jea;HAN Sang-Uk
分类号 H01L25/00;H01L25/065 主分类号 H01L25/00
代理机构 代理人
主权项 1. A method of fabricating a semiconductor device, the method comprising: arranging a plurality of first semiconductor chips, each having a first width, and a plurality of second semiconductor chips, each having a second width, to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, the first width of each of the first semiconductor chips being greater than the second width of each of the second semiconductor chips; forming a first molding layer surrounding the second semiconductor chips on the first wafer; forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips; arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate; and forming a second molding layer surrounding the chip package on the package substrate.
地址 Suwon-si KR