| 发明名称 |
Parasitic Capacitance Extraction for FinFETs |
| 摘要 |
A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer. |
| 申请公布号 |
US2014258962(A1) |
申请公布日期 |
2014.09.11 |
| 申请号 |
US201313873969 |
申请日期 |
2013.04.30 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Ho Chia-Ming;Su Ke-Ying;Chao Hsiao-Shu;Cheng Yi-Kan;Wu Ze-Ming;Lee Hsien-Hsin Sean |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
generating a three-dimensional table, wherein table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from a group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs), and wherein the three-dimensional table is indexed by:
poly-to-metal-contact spacings of the FinFETs;fin-to-fin spacings of the FinFETs; andmetal-contact-to-second-poly spacings of the FinFETs, wherein the step of generating the three-dimensional table is performed using a computer. |
| 地址 |
Hsin-Chu TW |
