SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST

摘要

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

主权项

1. A multilayer printed circuit board, comprising:
a first dielectric layer; a first plating resist selectively positioned in the first dielectric layer; a second plating resist selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist; and a through hole extending through the first dielectric layer, the first plating resist, and the second plating resist, where an interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist to form a partitioned plated through hole having a first via segment electrically isolated from a second via segment.