Apparatus and Method for Transitive Instruction Scheduling

摘要

A processor includes a multiple stage pipeline with a scheduler with a wakeup block and select logic. The wakeup block is configured to wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set. In a second cycle, the wakeup block wakes instructions dependent upon the wake instruction set to augment the wake instruction set. The select logic selects instructions from the wake instruction set based upon program order.

主权项

1. A processor, comprising:
a multiple stage pipeline including a scheduler with a wakeup block and select logic, wherein the wakeup block is configured to
wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set;wake, in a second cycle, instructions dependent upon the wake instruction set to augment the wake instruction set; and wherein the select logic selects instructions from the wake instruction set based upon program order.