摘要 |
<p>The invention relates to the switching from a first mode of operation to a second mode, of a first and a second cores of a processor of a processing device further comprising a controller. The controller sends a first message to the cores. Upon reception of the first message, sensible data handled by the cores are stored securely. The second core sends, to the first core, a second message indicating the completion of the step of storing its sensible data. Upon reception of the second message, the first core stores securely, in a storage unit, other sensible data, and, when finished, sends to the controller a third message. Upon reception of the third message, the controller sends to the first core a fourth message. Then, the first core sends a fifth message to the second core. Upon reception of the fourth and the fifth messages, the cores enter into the second mode.</p> |