发明名称 Method for fabricating semiconductor device with reduced Miller capacitance
摘要 A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench.
申请公布号 US8828822(B2) 申请公布日期 2014.09.09
申请号 US201213628055 申请日期 2012.09.27
申请人 Anpec Electronics Corporation 发明人 Lin Yung-Fa;Chang Chia-Hao
分类号 H01L21/336 主分类号 H01L21/336
代理机构 代理人 Hsu Winston;Margo Scott
主权项 1. A method for fabricating a semiconductor transistor device, comprising: providing a semiconductor substrate having a first conductivity type; forming an epitaxial layer on the semiconductor substrate; etching the epitaxial layer to thereby form a gate trench in the epitaxial layer; after forming the gate trench, forming a spacer on a sidewall of the epitaxial layer within the gate trench; etching the epitaxial layer from a bottom surface of the gate trench to form a recess underneath the gate trench; performing a thermal oxidation process to form an oxide layer that only fills up the recess; removing the spacer; forming a gate oxide layer on an exposed sidewall of the gate trench; and forming a gate in the gate trench.
地址 Hsinchu Science Park, Hsin-Chu TW