发明名称 |
Semiconductor memory device |
摘要 |
According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block. |
申请公布号 |
US8830751(B2) |
申请公布日期 |
2014.09.09 |
申请号 |
US201213424812 |
申请日期 |
2012.03.20 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Maejima Hiroshi;Hosono Koji |
分类号 |
G11C11/34;H01L27/088;G11C16/10;G11C16/04;G11C16/06;G11C16/08;G11C16/34;H01L27/115;H01L21/8234 |
主分类号 |
G11C11/34 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A semiconductor memory device comprising:
a plurality of memory cells stacked above a semiconductor substrate; a selection transistor; a memory string in which the plurality of memory cells are connected in series, and the selection transistor is connected in series with the memory cells; a block including a plurality of memory strings; a word line electrically coupled to a control gate of one of the memory cells; a select gate line electrically coupled to a gate of the selection transistor; a bit line electrically coupled to one of the memory cells; and a circuit configured to apply, in data write or read, a positive voltage to a select gate line of a selected memory string in a selected block, the circuit being configured to apply a negative voltage to a select gate line of an unselected memory string in the selected block, the circuit being configured to apply the negative voltage to a select gate line of an unselected block. |
地址 |
Tokyo JP |