发明名称 Multi-level contact to a 3D memory array and method of making
摘要 A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
申请公布号 US8828884(B2) 申请公布日期 2014.09.09
申请号 US201213478483 申请日期 2012.05.23
申请人 Sandisk Technologies Inc. 发明人 Lee Yao-Sheng;Chen Zhen;Fukata Syo
分类号 H01L21/467 主分类号 H01L21/467
代理机构 The Marbury Law Group PLLC 代理人 The Marbury Law Group PLLC
主权项 1. A method of making multi-level contacts, comprising: providing an in-process multilevel device comprising at least one device region and at least one contact region, the contact region comprising a plurality of electrically conductive layers configured in a step pattern; forming a conformal etch stop layer over the plurality of electrically conductive layers; forming a first electrically insulating layer over the etch stop layer; forming a conformal sacrificial layer over the first electrically insulating layer; forming a second electrically insulating layer over the sacrificial layer; etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers; wherein: the plurality of electrically conductive layers comprise at least a first conductive layer in a first device level located over a substrate and a second conductive layer in a second device level located higher than the first device level over the substrate; the first conductive layer comprises a first portion which laterally extends past the second conductive layer to form at least a portion of the step pattern; and the plurality of contact openings comprises a first contact opening which extends to the first portion of the first conductive layer and a second contact opening which extends to an upper surface of the second conductive layer; and further comprising forming a first electrically conductive contact in the first contact opening and a second electrically conductive contact in the second contact opening, wherein the first electrically conductive contact extends deeper than the second electrically conductive contact; wherein the step of etching comprises: using a first etch chemistry, selectively etching first portions of the plurality of the contact openings through the second electrically insulating layer using the sacrificial layer as an etch stop; using a second etch chemistry, selectively etching second portions of the plurality of the contact openings through the sacrificial layer using the first electrically insulating layer as an etch stop; using a third etch chemistry, selectively etching third portions of the plurality of the contact openings through the first electrically insulating layer using the conformal etch stop layer as an etch stop; and using a fourth etch chemistry, selectively etching fourth portions of the plurality of the contact openings through the conformal etch stop layer to reach the plurality of electrically conductive layers.
地址 Plano TX US