| 主权项 |
1. A manufacturing method of a semiconductor device comprising the steps of:
(a) providing a lead frame including a die pad comprised of a quadrangle having a pair of first sides opposed to each other and a pair of second sides intersecting with the first sides and opposed to each other, a first lead group arranged along one of the two first sides of the die pad in the plan view, a second lead group arranged along the other of the two first sides of the die pad in the plan view, and a plurality of suspending leads connecting to the second sides of the die pad, respectively; (b) mounting a first semiconductor chip having a first front surface, a plurality of first bonding pads formed on the first front surface, and a first back surface opposite to the first front surface, in a first area of the die pad, and mounting a second semiconductor chip having a second front surface, a plurality of second bonding pads formed on the second front surface, and a second back surface opposite to the second front surface, in a second area of the die pad positioned next to the first area in the plan view; (c) electrically connecting a plurality of external bonding pads of the first bonding pads and a plurality of external bonding pads of the second bonding pads with the first lead group and the second lead group via a plurality of external wires, respectively, and electrically connecting a plurality of internal bonding pads of the first bonding pads with a plurality of internal bonding pads of the second bonding pads via a plurality of internal wires; and (d) supplying resin from one side to the other side of the second sides of the die pad, and sealing the die pad, the first semiconductor chip, the second semiconductor chip, the external wires and the internal wires with the resin, wherein the second area is positioned between the first area and the other of the second sides of the die pad in the plan view, wherein the internal bonding pads of the first semiconductor chip include a first pad group and a second pad group, wherein the internal bonding pads of the second semiconductor chip include a third pad group and a fourth pad group, wherein the internal wires include a plurality of first internal wires electrically connecting the first pad group and the third pad group, respectively, and a plurality of second internal wires electrically connecting the second pad group and the fourth pad group, respectively, wherein a distance between the first pad group and the second pad group is larger than a distance between the third pad group and the fourth pad group, and wherein the distance between the first pad group and the second pad group is larger than the length of some of the internal bonding pads. |
